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Alif Semiconductor /AE302F40C1537LE_CM55_HP_View /M55HE_CFG /HE_CAMERA_PIXCLK

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Interpret as HE_CAMERA_PIXCLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)ENA 0 (Val_0x0)DIVISOR

DIVISOR=Val_0x0, ENA=Val_0x0

Description

LPCPI Pixel Clock Control Register

Fields

ENA

LPCPI pixel clock enable

0 (Val_0x0): Clock disabled

1 (Val_0x1): Clock enabled
DIVISOR

LPCPI pixel clock integer divisor n: Clock divided by n

0 (Val_0x0): Illegal values

1 (Val_0x1): Illegal values

2 (Val_0x2): Clock divided by 2

3 (Val_0x3): Clock divided by 3

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data